PWM control of a three-phase inverter using FPGA board

Description of the open EMP1270 card

EPM1270:embedded CPLD device equipped with:Operating frequency: 50MHz, Operating Voltage: 1.5 3.3V,Package: QFP144, I/O: 116, LEs: 1,270, the equivalent of 4,000 logic gates, Debugging programming: JTAG, AMS1117-3.3: 3.3 V voltage regulator.

FPGA board

The architecture of the PWM control of the inverter in VHDL

The processes run in parallel in VHDL.

The architecture of the MLI command

Frequency divider:

The asynchronous counter is based on the frequency divider. It is a simple D flip-flop whose inverted output is sent to its D input. Thus, at each rising edge of the clock input, the data transferred to the output is complemented

Frequency divider

The frequency of EPM1270 is 50 MHz, the value we need at the output is equal to the frequency of the triangular signal from PART 1, which is 2 kHz. output is equal to the frequency of the triangular signal from PART 1, which is 2 kHz.
So we will divide the 50 MHz by 2 kHz to obtain the value of div clock. =25,000.So the falg signal is at a frequency of 2 kHz as indicated by the code below. below

The Duty cycle block:

The system clock divided by the PWM frequency is equal to the number of clock impulses in a PWM period. System clock pulses in a PWM period. The counters define this PWM period for each phase. There is a counter for each PWM phase, with their values staggered by phase. Each counter increments on each system clock and resets once it has reached the end of its period.

The duty cycle determines the points during the period where the rising edges and descending edges of the PWM signal occur. Figure 2 illustrates the basic concept used to determine these positions. The falling edge of the signal occurs at service cycle of , and its rising edge occurs at the end of the period minus one half service cycle. Once the counter reaches each of these positions, the PWM signal is switched accordingly. Since a half-cycle can never exceed a half-period, the descending front always occurs before the ascending front.

the Cyclical Report.

The frequency of the sinusoidal signal in PART 1 is equal to 50 Hz and compare with the triangular signal of frequency 2 kHz. So the number of impulses in one period of the sinusoidal signal is nbr=2000/50 = 40 pulses, this is the value of resolution.

In our program that we have developed, the value of the cursor is initially initially equal to 0 and will increment each time up to the maximum value of 20 and then it decrements down to 0 and so on.as indicated in the code below

The blockPhase in PWM:

We divide the card's frequency of 50 MHz by 1249 and then by 20 to obtain at the output, a frequency equal to 2 kHz. To force a single pulse in a period equal to 1/2000 = 0.5 ms.

The offset between the signals:

Each signal is shifted by 1/3 of the Sin period, shift = 1/31/50 = 6.666 ms
The period of the output PWM signal is equal to T=1/F=1/2000 = 0.5 ms so the number of shifted pulses Nbr = Tdecal / (F output) = 6.666 / 0.5 = 13.333 pulse

The block Phase in PWM:

We divide the frequency of the 50 MHz board by 1249 and then by 20 to obtain at the output, a frequency equal to 2 kHz. To force a single pulse in a period equal to 1/2000 = 0.5 ms.

The offset between the signals:

Between signal A and B, 13.333 impulses; between B and C, 13.333; therefore, between A and C
13.332 = 26.66 impulse,

to solve this problem we initially declare signal duty cycle 2 of signal B to 13 ("01101"bin) as a value to send to val cur 2 of the PWM, and for the 0.33 offset, we will initially declare the signal of the counter cnt 2 with a value equal to 0.33 Tsin=0.3340 =13 ("00110" bin)

Finally, the offset between A and C is (26.66 pulses), for the offset of 0.66 follows the same principle;

we will initially declare the signal of counter cnt 3 to a value equal to 0.66 Tsin = 0.6640 = 26 ("00110" bin), and for the shift of 26 reverse the Duty Cycle 3 process of signal C to perform the decrement before incrementing the value of Duty Cycle 3, we have already shifted by 20 pulses and for the remaining 6, we initially set the duty cycle 3 signal to 19-6=13 ("01101"bin) as a value to send to val cur 3 of the PWM.

Complete code:

Choice of pins

Pin selection block

The maximum voltage that can be reached by the board is 3.3 V and 16 mA.
By default, the clock pin is Pin 18.
We chose the successive pins 119, 121, 123, 111, 113, 117.

Electrical schematic of the inverter with Eagle.

The output signals:

The output signal of our system that will be used to control the moments of
switching of the three-phase inverter switches:

signal de sortie.

Thanks for reading!

Projects

Search This Blog